From 4fb21fb4bf9d35179340d30654202eb6d7f7bb0f Mon Sep 17 00:00:00 2001 From: m Date: Sat, 28 Aug 2021 00:11:18 +0200 Subject: [PATCH] Renaming project and files from first* to inverter* --- first-cache.lib => inverter_proto-cache.lib | 0 first.kicad_pcb => inverter_proto.kicad_pcb | 0 first.pro => inverter_proto.pro | 0 first.sch => inverter_proto.sch | 0 inverter_proto.sch-bak | 420 ++++++++++++++++++ ...b => inverter_proto_experimental-cache.lib | 0 ...tal.sch => inverter_proto_experimental.sch | 0 ...bak => inverter_proto_experimental.sch-bak | 0 8 files changed, 420 insertions(+) rename first-cache.lib => inverter_proto-cache.lib (100%) rename first.kicad_pcb => inverter_proto.kicad_pcb (100%) rename first.pro => inverter_proto.pro (100%) rename first.sch => inverter_proto.sch (100%) create mode 100644 inverter_proto.sch-bak rename first_experimental-cache.lib => inverter_proto_experimental-cache.lib (100%) rename first_experimental.sch => inverter_proto_experimental.sch (100%) rename first_experimental.sch-bak => inverter_proto_experimental.sch-bak (100%) diff --git a/first-cache.lib b/inverter_proto-cache.lib similarity index 100% rename from first-cache.lib rename to inverter_proto-cache.lib diff --git a/first.kicad_pcb b/inverter_proto.kicad_pcb similarity index 100% rename from first.kicad_pcb rename to inverter_proto.kicad_pcb diff --git a/first.pro b/inverter_proto.pro similarity index 100% rename from first.pro rename to inverter_proto.pro diff --git a/first.sch b/inverter_proto.sch similarity index 100% rename from first.sch rename to inverter_proto.sch diff --git a/inverter_proto.sch-bak b/inverter_proto.sch-bak new file mode 100644 index 0000000..49b9103 --- /dev/null +++ b/inverter_proto.sch-bak @@ -0,0 +1,420 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE Vcc +U 1 1 6064C406 +P 1050 2200 +F 0 "Vcc" H 1278 2246 50 0000 L CNN +F 1 "20" H 1278 2155 50 0000 L CNN +F 2 "" H 1050 2200 50 0001 C CNN +F 3 "~" H 1050 2200 50 0001 C CNN + 1 1050 2200 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR? +U 1 1 6064E58B +P 1050 6200 +F 0 "#PWR?" H 1050 5950 50 0001 C CNN +F 1 "GND" H 1055 6027 50 0000 C CNN +F 2 "" H 1050 6200 50 0001 C CNN +F 3 "" H 1050 6200 50 0001 C CNN + 1 1050 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 1900 1050 1100 +Connection ~ 3350 1550 +Wire Wire Line + 4450 1550 3350 1550 +Wire Wire Line + 4750 1350 4750 1100 +$Comp +L Transistor_BJT:2N3905 Q12 +U 1 1 60F7E2F2 +P 4650 1550 +F 0 "Q12" H 4840 1504 50 0000 L CNN +F 1 "2N3905" H 4840 1595 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 4850 1475 50 0001 L CIN +F 3 "https://www.nteinc.com/specs/original/2N3905_06.pdf" H 4650 1550 50 0001 L CNN +F 4 "Q" H 4650 1550 50 0001 C CNN "Spice_Primitive" +F 5 "bdx54c" H 4650 1550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4650 1550 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/m/projects/electronics/ngspice_models/bdx54c.lib" H 4650 1550 50 0001 C CNN "Spice_Lib_File" + 1 4650 1550 + 1 0 0 1 +$EndComp +Wire Wire Line + 3350 1250 3350 1100 +$Comp +L Device:R Rpu1 +U 1 1 60F79F09 +P 3350 1400 +F 0 "Rpu1" H 3420 1446 50 0000 L CNN +F 1 "100k" H 3420 1355 50 0000 L CNN +F 2 "" V 3280 1400 50 0001 C CNN +F 3 "~" H 3350 1400 50 0001 C CNN + 1 3350 1400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 1100 3350 1100 +Wire Wire Line + 1900 1900 2200 1900 +Connection ~ 3350 1100 +Wire Wire Line + 3350 1100 4750 1100 +Wire Wire Line + 3350 1550 3350 1700 +Connection ~ 1050 2950 +Wire Wire Line + 1900 1900 1900 2150 +Wire Wire Line + 1050 2950 1900 2950 +Wire Wire Line + 1900 2750 1900 2950 +Connection ~ 1900 2950 +Text GLabel 1900 1900 0 50 Input ~ 0 +V11 +$Comp +L Transistor_BJT:2N2219 Q11 +U 1 1 60F73E70 +P 3250 1900 +F 0 "Q11" H 3440 1946 50 0000 L CNN +F 1 "2N2219" H 3440 1855 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-39-3" H 3450 1825 50 0001 L CIN +F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 3250 1900 50 0001 L CNN +F 4 "Q" H 3250 1900 50 0001 C CNN "Spice_Primitive" +F 5 "2N2219" H 3250 1900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3250 1900 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/m/projects/electronics/ngspice_models/2N2219.LIB" H 3250 1900 50 0001 C CNN "Spice_Lib_File" + 1 3250 1900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 2950 1050 6200 +Wire Wire Line + 1050 2600 1050 2950 +Wire Wire Line + 1050 2500 1050 2950 +Connection ~ 1050 6200 +Wire Wire Line + 8700 5400 8700 6200 +Wire Wire Line + 7250 5200 7250 5350 +Text GLabel 7250 5200 0 50 Input ~ 0 +V22 +Wire Wire Line + 7250 5200 7650 5200 +$Comp +L Transistor_BJT:2N2219 Q4 +U 1 1 60FB5A31 +P 8600 5200 +F 0 "Q4" H 8790 5246 50 0000 L CNN +F 1 "2N2219" H 8790 5155 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-39-3" H 8800 5125 50 0001 L CIN +F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 8600 5200 50 0001 L CNN +F 4 "Q" H 8600 5200 50 0001 C CNN "Spice_Primitive" +F 5 "2N2219" H 8600 5200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8600 5200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/m/projects/electronics/ngspice_models/2N2219.LIB" H 8600 5200 50 0001 C CNN "Spice_Lib_File" + 1 8600 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7250 6200 8700 6200 +Connection ~ 7250 6200 +Wire Wire Line + 7250 6200 7250 5950 +Wire Wire Line + 1050 6200 1900 6200 +Connection ~ 1900 6200 +Wire Wire Line + 1900 6200 1900 5950 +Connection ~ 4750 1100 +Wire Wire Line + 4750 1100 8700 1100 +Wire Wire Line + 10150 1350 10150 1100 +Wire Wire Line + 8700 1250 8700 1100 +Connection ~ 8700 1100 +Wire Wire Line + 8700 1100 10150 1100 +Wire Wire Line + 9850 1550 8700 1550 +$Comp +L Transistor_BJT:2N3905 Q22 +U 1 1 60F9BAB5 +P 10050 1550 +F 0 "Q22" H 10240 1504 50 0000 L CNN +F 1 "2N3905" H 10240 1595 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-92_Inline" H 10250 1475 50 0001 L CIN +F 3 "https://www.nteinc.com/specs/original/2N3905_06.pdf" H 10050 1550 50 0001 L CNN +F 4 "Q" H 10050 1550 50 0001 C CNN "Spice_Primitive" +F 5 "bdx54c" H 10050 1550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 10050 1550 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/m/projects/electronics/ngspice_models/bdx54c.lib" H 10050 1550 50 0001 C CNN "Spice_Lib_File" + 1 10050 1550 + 1 0 0 1 +$EndComp +$Comp +L Device:R Rpu2 +U 1 1 60F9BABC +P 8700 1400 +F 0 "Rpu2" H 8770 1446 50 0000 L CNN +F 1 "101k" H 8770 1355 50 0000 L CNN +F 2 "" V 8630 1400 50 0001 C CNN +F 3 "~" H 8700 1400 50 0001 C CNN + 1 8700 1400 + 1 0 0 -1 +$EndComp +$Comp +L Transistor_BJT:2N2219 Q21 +U 1 1 60F9BAC6 +P 8600 1900 +F 0 "Q21" H 8790 1946 50 0000 L CNN +F 1 "2N2219" H 8790 1855 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-39-3" H 8800 1825 50 0001 L CIN +F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 8600 1900 50 0001 L CNN +F 4 "Q" H 8600 1900 50 0001 C CNN "Spice_Primitive" +F 5 "2N2219" H 8600 1900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8600 1900 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/m/projects/electronics/ngspice_models/2N2219.LIB" H 8600 1900 50 0001 C CNN "Spice_Lib_File" + 1 8600 1900 + 1 0 0 -1 +$EndComp +Connection ~ 8700 1550 +Wire Wire Line + 8700 1550 8700 1700 +Wire Wire Line + 7250 1900 7250 2150 +Wire Wire Line + 7250 2750 7250 2950 +Wire Wire Line + 7250 2950 8700 2950 +Connection ~ 7250 2950 +Wire Wire Line + 8700 2100 8700 2950 +Text GLabel 7250 1900 0 50 Input ~ 0 +V12 +Wire Wire Line + 1900 6200 3350 6200 +Connection ~ 3350 6200 +Wire Wire Line + 3350 5500 3350 6200 +Wire Wire Line + 1900 5300 1900 5350 +Text GLabel 1900 5300 0 50 Input ~ 0 +V21 +Wire Wire Line + 1900 5300 2250 5300 +$Comp +L Transistor_BJT:2N2219 Q3 +U 1 1 60FABDE3 +P 3250 5300 +F 0 "Q3" H 3440 5346 50 0000 L CNN +F 1 "2N2219" H 3440 5255 50 0000 L CNN +F 2 "Package_TO_SOT_THT:TO-39-3" H 3450 5225 50 0001 L CIN +F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 3250 5300 50 0001 L CNN +F 4 "Q" H 3250 5300 50 0001 C CNN "Spice_Primitive" +F 5 "2N2219" H 3250 5300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3250 5300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/m/projects/electronics/ngspice_models/2N2219.LIB" H 3250 5300 50 0001 C CNN "Spice_Lib_File" + 1 3250 5300 + 1 0 0 -1 +$EndComp +Text Notes 600 7550 0 50 ~ 0 +.tran 50p 250u +$Comp +L pspice:VSOURCE V21 +U 1 1 60FABDEA +P 1900 5650 +F 0 "V21" H 2128 5696 39 0000 L CNN +F 1 "PULSE(0 5 120u 1n 1n 100u 0 0)" H 2128 5605 39 0000 L CNN +F 2 "" H 1900 5650 39 0001 C CNN +F 3 "~" H 1900 5650 39 0001 C CNN + 1 1900 5650 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V22 +U 1 1 60FB5A38 +P 7250 5650 +F 0 "V22" H 7478 5696 39 0000 L CNN +F 1 "PULSE(0 5 10u 1n 1n 100u 0 0)" H 7478 5605 39 0000 L CNN +F 2 "" H 7250 5650 39 0001 C CNN +F 3 "~" H 7250 5650 39 0001 C CNN + 1 7250 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 6200 7250 6200 +Wire Wire Line + 3350 4800 3350 5100 +Wire Wire Line + 3350 4800 4750 4800 +Connection ~ 4750 4800 +Wire Wire Line + 4750 4800 5250 4800 +Wire Wire Line + 8700 3300 8700 5000 +$Comp +L pspice:VSOURCE V12 +U 1 1 60FA5ACD +P 7250 2450 +F 0 "V12" H 7478 2496 39 0000 L CNN +F 1 "PULSE(0 5 120u 1n 1n 100u 0 0)" H 7478 2405 39 0000 L CNN +F 2 "" H 7250 2450 39 0001 C CNN +F 3 "~" H 7250 2450 39 0001 C CNN + 1 7250 2450 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V11 +U 1 1 6064E251 +P 1900 2450 +F 0 "V11" H 2128 2496 39 0000 L CNN +F 1 "PULSE(0 5 10u 1n 1n 100u 0 0)" H 2128 2405 39 0000 L CNN +F 2 "" H 1900 2450 39 0001 C CNN +F 3 "~" H 1900 2450 39 0001 C CNN + 1 1900 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 3850 5250 3300 +Wire Wire Line + 5250 3300 8700 3300 +Connection ~ 8700 3300 +Wire Wire Line + 8700 3300 10150 3300 +$Comp +L Device:Transformer_1P_1S T1 +U 1 1 60F92E27 +P 5650 4050 +F 0 "T1" H 5650 4407 39 0000 C CNN +F 1 "Transformer_1P_1S" H 5650 4332 39 0000 C CNN +F 2 "" H 5650 4050 39 0001 C CNN +F 3 "~" H 5650 4050 39 0001 C CNN +F 4 "X" H 5650 4050 50 0001 C CNN "Spice_Primitive" +F 5 "IT" H 5650 4050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5650 4050 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/m/projects/electronics/ngspice_models/ideal_transformer.mod" H 5650 4050 50 0001 C CNN "Spice_Lib_File" +F 8 "1 2 4 3" H 5650 4050 50 0001 C CNN "Spice_Node_Sequence" + 1 5650 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4250 5250 4800 +$Comp +L Device:R R_Load +U 1 1 60F942BC +P 6500 4050 +F 0 "R_Load" H 6570 4096 50 0000 L CNN +F 1 "2k" H 6570 4005 50 0000 L CNN +F 2 "" V 6430 4050 50 0001 C CNN +F 3 "~" H 6500 4050 50 0001 C CNN + 1 6500 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 3850 6500 3900 +Wire Wire Line + 6500 4200 6500 4250 +Wire Wire Line + 6500 4250 6050 4250 +$Comp +L power:GND #PWR? +U 1 1 60F9706B +P 6500 4250 +F 0 "#PWR?" H 6500 4000 50 0001 C CNN +F 1 "GND" H 6505 4077 50 0000 C CNN +F 2 "" H 6500 4250 50 0001 C CNN +F 3 "" H 6500 4250 50 0001 C CNN + 1 6500 4250 + 1 0 0 -1 +$EndComp +Connection ~ 6500 4250 +Text GLabel 6500 3850 2 50 Input ~ 0 +V_load +Wire Wire Line + 6050 3850 6500 3850 +Wire Wire Line + 1900 2950 3350 2950 +Connection ~ 3350 2950 +Wire Wire Line + 3350 2950 7250 2950 +Wire Wire Line + 10150 1750 10150 3300 +Wire Wire Line + 3350 2100 3350 2950 +$Comp +L Device:R R_b11 +U 1 1 60FA7473 +P 2350 1900 +F 0 "R_b11" V 2143 1900 50 0000 C CNN +F 1 "100" V 2234 1900 50 0000 C CNN +F 2 "" V 2280 1900 50 0001 C CNN +F 3 "~" H 2350 1900 50 0001 C CNN + 1 2350 1900 + 0 1 1 0 +$EndComp +Wire Wire Line + 2500 1900 3050 1900 +$Comp +L Device:R R_b12 +U 1 1 60FAC87E +P 7750 1900 +F 0 "R_b12" V 7543 1900 50 0000 C CNN +F 1 "100" V 7634 1900 50 0000 C CNN +F 2 "" V 7680 1900 50 0001 C CNN +F 3 "~" H 7750 1900 50 0001 C CNN + 1 7750 1900 + 0 1 1 0 +$EndComp +Wire Wire Line + 7250 1900 7600 1900 +Wire Wire Line + 7900 1900 8400 1900 +$Comp +L Device:R R_b22 +U 1 1 60FB05BB +P 7800 5200 +F 0 "R_b22" V 7593 5200 50 0000 C CNN +F 1 "100" V 7684 5200 50 0000 C CNN +F 2 "" V 7730 5200 50 0001 C CNN +F 3 "~" H 7800 5200 50 0001 C CNN + 1 7800 5200 + 0 1 1 0 +$EndComp +$Comp +L Device:R R_b21 +U 1 1 60FB24E9 +P 2400 5300 +F 0 "R_b21" V 2193 5300 50 0000 C CNN +F 1 "100" V 2284 5300 50 0000 C CNN +F 2 "" V 2330 5300 50 0001 C CNN +F 3 "~" H 2400 5300 50 0001 C CNN + 1 2400 5300 + 0 1 1 0 +$EndComp +Wire Wire Line + 2550 5300 3050 5300 +Wire Wire Line + 7950 5200 8400 5200 +Wire Wire Line + 4750 1750 4750 4800 +$EndSCHEMATC diff --git a/first_experimental-cache.lib b/inverter_proto_experimental-cache.lib similarity index 100% rename from first_experimental-cache.lib rename to inverter_proto_experimental-cache.lib diff --git a/first_experimental.sch b/inverter_proto_experimental.sch similarity index 100% rename from first_experimental.sch rename to inverter_proto_experimental.sch diff --git a/first_experimental.sch-bak b/inverter_proto_experimental.sch-bak similarity index 100% rename from first_experimental.sch-bak rename to inverter_proto_experimental.sch-bak