inv-schematics/inverter_proto_experimental.sch

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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L pspice:VSOURCE Vin
U 1 1 605607CB
P 1100 3850
F 0 "Vin" H 1328 3896 50 0000 L CNN
F 1 "50" H 1328 3805 50 0000 L CNN
F 2 "" H 1100 3850 50 0001 C CNN
F 3 "~" H 1100 3850 50 0001 C CNN
1 1100 3850
1 0 0 -1
$EndComp
Text Notes 600 7550 0 50 ~ 0
.tran 1us 100ms
Wire Wire Line
3100 2150 3100 1750
Wire Wire Line
3050 2800 3100 2800
Wire Wire Line
3100 2800 3100 2750
Connection ~ 3100 2800
Text GLabel 3100 1750 0 50 Input ~ 0
Vb_highside
Wire Wire Line
1100 850 1100 3550
$Comp
L Transistor_BJT:BCX53 Q2
U 1 1 60653B03
P 6100 1500
F 0 "Q2" H 6291 1454 50 0000 L CNN
F 1 "BCX53" H 6291 1545 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-89-3" H 6300 1425 50 0001 L CIN
F 3 "http://www.infineon.com/dgdl/bcx51_bcx52_bcx53.pdf" H 6100 1500 50 0001 L CNN
F 4 "Q" H 6100 1500 50 0001 C CNN "Spice_Primitive"
F 5 "BCX53/SIE" H 6100 1500 50 0001 C CNN "Spice_Model"
F 6 "Y" H 6100 1500 50 0001 C CNN "Spice_Netlist_Enabled"
F 7 "siemens.lib" H 6100 1500 50 0001 C CNN "Spice_Lib_File"
1 6100 1500
1 0 0 1
$EndComp
$Comp
L Device:R R3
U 1 1 6065633A
P 5450 1500
F 0 "R3" V 5243 1500 50 0000 C CNN
F 1 "500" V 5334 1500 50 0000 C CNN
F 2 "" V 5380 1500 50 0001 C CNN
F 3 "~" H 5450 1500 50 0001 C CNN
1 5450 1500
0 1 1 0
$EndComp
Wire Wire Line
1100 5950 3100 5950
Wire Wire Line
1100 4150 1100 5950
Wire Wire Line
6200 2500 6200 5950
Wire Wire Line
6200 1300 6200 850
Wire Wire Line
3100 2800 3100 5950
Connection ~ 3100 5950
$Comp
L power:GND #PWR?
U 1 1 6065CC42
P 1100 5950
F 0 "#PWR?" H 1100 5700 50 0001 C CNN
F 1 "GND" H 1105 5777 50 0000 C CNN
F 2 "" H 1100 5950 50 0001 C CNN
F 3 "" H 1100 5950 50 0001 C CNN
1 1100 5950
1 0 0 -1
$EndComp
Connection ~ 1100 5950
Wire Wire Line
6200 1700 6200 2200
Wire Wire Line
5900 1500 5600 1500
$Comp
L pspice:VSOURCE Vb
U 1 1 605670B8
P 3100 2450
F 0 "Vb" H 3328 2496 50 0000 L CNN
F 1 "PULSE(50 25 10m 1u 1u 20m 0 0)" H 3328 2405 50 0000 L CNN
F 2 "" H 3100 2450 50 0001 C CNN
F 3 "~" H 3100 2450 50 0001 C CNN
1 3100 2450
1 0 0 -1
$EndComp
Text GLabel 5800 1500 1 50 Input ~ 0
V_Q2_b
Wire Wire Line
1100 850 6200 850
Wire Wire Line
3100 5950 6200 5950
$Comp
L Device:R Rl
U 1 1 60674F8A
P 6200 2350
F 0 "Rl" H 6270 2396 50 0000 L CNN
F 1 "1k" H 6270 2305 50 0000 L CNN
F 2 "" V 6130 2350 50 0001 C CNN
F 3 "~" H 6200 2350 50 0001 C CNN
1 6200 2350
1 0 0 -1
$EndComp
Wire Wire Line
3100 1750 5300 1750
Wire Wire Line
5300 1750 5300 1500
Text GLabel 6200 2000 0 50 Input ~ 0
V_load
$EndSCHEMATC